Specifically, the present invention relates to an electronic circuit arrangement having an electronic circuit module constructed from one or more electronic circuit units, the electronic circuit units in each case having a control input terminal for activating or deactivating the relevant electronic circuit unit by means of a select signal and a drive line assigned to each electronic circuit unit and serving for feeding the select signal to each electronic circuit unit. A select signal generating unit for generating the select signal and a connecting line for connecting each electronic circuit unit to the select signal generating unit are furthermore provided.
FIG. 2 shows a conventional electronic circuit module M constructed from individual electronic chips BS1, BS2, BS3, . . . BSn. The chips BS1-BSn are constructed as memory chips, for example, which in their entirety form a memory module.
Such integrated circuit modules with memory chips are currently of great importance for data storage. The increasing demand for larger storage capacities requires ever more chips to be accommodated in a single module M.
In a conventional manner, each chip BS1-BSn is driven or activated/deactivated via a dedicated drive line L1, L2, L3 . . . Ln. Such activation/deactivation lines are led to a specific terminal of each chip, the so-called chip select terminal CS1, CS2, CS3 . . . CSn (CS=“Chip-Select”). If an activation signal (also referred to as select signal) is applied to a chip select input of a chip, then all remaining terminal pins are activated in this chip.
One disadvantage of the conventional circuit arrangement as is shown by way of example in FIG. 2 is that each chip select terminal has to be routed via a separate line to outside the memory module M in order to be respectively accessible via a terminal A1, A2, A3 . . . An. Consequently, the memory module disadvantageously has to have a large number of lines L1-Ln and a corresponding number of input terminals E1, E2, E3, . . . En in order that each chip BS1-BSn can actually be addressed separately. Against the background of an increasing demand for storage capacities, more and more electronic chips BS1-BSn that are designed as memory chips, for example, are necessary.
Since the space requirement of a circuit arrangement of this type is not permitted to increase substantially, the need arises to route a drive line L1-Ln out of the module M in each case for each individual chip BS1-BSn, a major problem with regard to wiring complexity and space requirement. Particularly in the case of complex circuit arrangements with the electronic chips BS1-BSn designed in a stacked construction, it is extremely disadvantageous that the corresponding select signal has to be fed to the module M separately for each individual chip BS1-BSn via separate lines L1-Ln.